Multilayer CMOS APS sensors integrated in CMOS vertical scale technology (3D) for particle detection
In this paper we suggest a novel approach to particle track reconstruction in vertex detectors. Vertical scale integration (3D) technology for the fabrication of CMOS VLSI circuits has been used to devise a low-material monolithic stack of sensitive pixellated layers connected through silicon vias (TSV) connections. The structure has been extensively simulated, has been designed in a conventional VLSI design flow and is currently under production: first prototypes will be available at the beginning of 2010.
A. Marras , “Multilayer CMOS APS sensors integrated in CMOS vertical scale technology (3D) for particle detection” presented at the 7th International Meeting on Front-End Electronics Montauk, New York (USA).