Scaled CMOS Technology
Technology Scaling and Its Limits
Over the past three decades, CMOS technology scaling has been a primary driver of the electronics industry and has provided a path toward both denser and faster integration [1-5]. The transistors manufactured today are 20 times faster and occupy less than 1% of the area of those built 20 years ago.
The number of devices per chip and the system performance has been improving exponentially over the last two decades. As the channel length is reduced, the performance improves, the power per switching event decreases, and the density improves. But the power density, total circuits per chip, and the total chip power consumption has been increasing.
The need for more performance and integration has accelerated the scaling trends in almost every device parameter, such as lithography, effective channel length, gate dielectric thickness, supply voltage, device leakage, etc.
Some of these parameters are approaching fundamental limits, and alternatives to the existing material and structures may need to be identified in order to continue scaling.
1.1 MOS scaling theory
During the early 1970s, both Mead  and Dennard  noted that the basic MOS transistor structure could be scaled to smaller physical dimensions. The scaling theory developed by Mead and Dennard allows a “photocopy reduction” approach to feature size reduction in CMOS technology, and while the dimensions shrink, scaling theory causes the field strengths in the MOS transistor to remain the same across different process generations.
Thus, the “original” form of scaling theory is constant field scaling. Constant field scaling requires a reduction of the power supply voltage with each technology generation. In the 1980s, CMOS adopted the 5V power supply, which was compatible with the power supply of bipolar TTL logic.
Constant field scaling was replaced with constant voltage scaling, and instead of remaining constant, the fields inside the device increased from generation to generation until the early 1990s, when excessive power dissipation and heating, gate dielectrics TDDB and channel hot carrier aging caused serious problems with the increasing electric field. As a result, constant field scaling was applied to technology scaling in the 1990s.
1.2 Moore’s Law
It was the realization of scaling theory and its usage in practice which has made possible the better-known “Moore’s Law.” Moore’s Law is a phenomenological observation that the number of transistors on integrated circuits doubles every two years, as shown in Figure 1.
It is intuitive that Moore’s Law cannot be sustained forever. However, predictions of size reduction limits due to material or design constraints, or even the pace of size reduction, have proven to elude the most insightful scientists.
Figure 1 Moore’s Law
1.3 Scaling to its limits
There does not seem to be any fundamental physical limitation that would prevent Moore’s Law from characterizing the trends of integrated circuits.
However, sustaining this rate of progress is not a straightforward achievement . Figure 2 shows the trends of power supply voltage, threshold voltage, and gate oxide thickness versus channel length for high performance CMOS logic technologies.
Sub-threshold non-scaling and standby power limitations bound the threshold voltage to a minimum of 0.2 V at the operating temperature. Thus, a significant reduction in performance gains is predicted below 1.5 V due to the fact that the threshold voltage decreases more slowly than the historical trend, leading to more aggressive device designs at higher electric fields.
Figure 2. Trends of power supply voltage Vdd, threshold voltage Vth, and gate oxide thickness tox, versus channel length for CMOS logic technologies.
Further technology scaling requires major changes in many areas, including: 1) improved lithography techniques and non-optical exposure technologies; 2) improved transistor design to achieve higher performance with smaller dimensions; 3) migration from current bulk CMOS devices to novel materials and structures, including silicon-on- insulator, strained Si and novel dielectric materials; 4) circuit sensitivity to soft errors from radiation; 5) smaller wiring for on-chip interconnection of the circuits; 6) stable circuits; 7) more productive design automation tools.
In addition, packaging technology needs to progress at a rate consistent with on- going CMOS technology scaling at sustainable cost/performance levels. This requires advances in I/O density, bandwidth, power distribution, and heat extraction. System architecture will also be required to maximize the performance gains achieved in advanced CMOS and packaging technologies.
1.4 Scaling impact on circuit performance
Transistor scaling is the primary factor in achieving high-performance microprocessors and memories.
Each 30% reduction in CMOS IC technology node scaling has 1) reduced the gate delay by 30% allowing an increase in maximum clock frequency of 43%; 2) doubled the device density; 3) reduced the parasitic capacitance by 30%; and 4) reduced energy and active power per transition by 65% and 50%, respectively.
Figure 3 shows CMOS performance, power density and circuit density trends, indicating a linear circuit performance as a result of technology scaling.
Figure 3 CMOS performance, power density and circuit density trends
- 1. C. Mead, “Fundamental limitations in microelectronics – I. MOS technology,” Solid State Electronics, vol. 15, pp. 819–829, 1972.
- 2. R. H. Dennard, F. H. Gaensslen, H-N, Yu, V.I. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE Journal of Solid-State Circuits, SC-9, pp.256–268, 1974.
- 3. H. Iwai, “CMOS Scaling towards its Limits,” IEEE, pp. 31–34, 1998.
- 4. R.D. Isaac, “Reaching the Limits of CMOS Technology,” IEEE, pp. 3, 1998
- 5. S. Borkar, “Design Challenges of Technology Scaling,” IEEE Micro, pp. 23–29, 1999.